This invention is related generally to packaging solid state image sensors, and more particularly, to the fabrication of a structure consisting of cover fully integrated to charge-coupled devices.
Charge-coupled devices (CCD) are image sensors formed by an array of light detecting devices built in a substrate. Most commonly, the array consists of MOS deep well devices built on a single crystal silicon substrate. Subsequently, the CCDs are mounted in a package that dispenses physical and chemical protection from the environment and provides a way for transferring input and output signals.
Typical CCD devices have a unique packaging and wiring configuration, unlike other semiconductor chips and packages. The package includes a glass cover plate so that light can pass through, thus impinging upon the CCD elements, which performs an analog (light) to-digital conversion. The CCD operation then moves the newly formed digitized element to an external support I/O circuitry for further processing. Since the I/Os cause interference between the analog inputs (i.e., the CCD elements), are typically placed on the periphery of the chip, typically outside of the field of the CCD analog interface. This creates a unique wiring constraint in that the I/O off-chip interface is restricted to one or more edges of the completed chip. A CCD I/O count is unlike that of a DRAM or a microprocessor, where data streams on a single bus and the I/O count is on the order of 30 interconnects, implying that the chip is not I/O bound. Practitioners in the art will realize that, as a result, the lithography, etch, and metallization groundrules for the I/O lines are significantly relaxed. For example, considering today digital cameras employing four mega pixels, a typical CCD image input has a width on the order of 0.7 cm. Clearly, thirty 100-200 um lines on a pitch of 300 um are not constrained by the size of the chip.
CCDs are commonly used in digital cameras, where maximum image resolution and minimum package size is highly desired. The highest resolution is achieved by maximizing the density of devices on the CCD, and minimizing the size of the package, which is accomplished by making the package of the same size as the CCD chip.
In a conventional CCD manufacturing line, a plurality of CCDs having dimensions on the order of 10 by 10 mm is produced on a silicon wafer, typically 200 mm in diameter. The wafer undergoes backside grinding to thin the wafer to a desired thickness. The wafer is then diced in order to separate the CCDs from each other, and each CCD is individually picked from the wafer and placed in a separate package. The front of the CCD, i.e., the side having the image sensing devices, faces up to be exposed to the opening in the package. Wire bonds connect the circuits on the CCD to metal leads on the package, providing a way of sending signals between the sensor and the larger apparatus on which the package is mounted. The wire bonds are of the order of 1 mm in length, and the set of bond wires occupy several square millimeters of package space. As the resolution of CCDs increases more I/Os are needed, increasing the proportion of the area of the package devoted to wiring, and decreasing the ratio of CCD to package size. After wire bonding is complete, the optically clear cover, such as glass, is typically mounted at the opening in the front of the package.
Several packages for solid state image sensors have been proposed in the past. In U.S. Pat. No. 4,760,470 to Stansbury, there is described a multilayer electrical interconnection structure having a wafer provided with CCDs that are back ground and diced into individual units. CCDs are handled individually and mounted face down over the opening of a base plate which has previously defined electrical conductors. Bond wires form an electrical connection from the CCD to the base plate conductors. A window is mounted to the front surface of the base plate for physical and chemical protection of the CCD. A cover that extends over the CCD is mounted to the back of the base plate. The cover is wider than the CCD, and the base plate extends beyond the cover, so that external conductors can be connected to the base plate conductors.
In U.S. Pat. No. 5,321,204 to Ko, there is described another type of package for solid state image sensors. Therein, CCDs are individually mounted on a ceramic substrate consisting of one or more conductive and dielectric layers. Wires are bonded to bond pads on the chip and to the corresponding lead of the lead frame. A glass cover is attached to the front of the package. The package is substantially wider and thicker than the CCD die mounted to it to accommodate the bond wires.
A second type of package known as Tape Automated Bonding (TAB) is also described in the previously mentioned reference. The inner leads are separated from the outer leads, and bonding bumpers are formed at the free ends of the inner leads. The tape is laid on a single CCD die, such that the bumpers rest on the chip bond pads. The two are thermally press bonded, connecting the chip to the leads. An insulation with a through hole is formed on the outer end of each inner lead. The through hole is filled with conductive material and an outer lead is then attached. Thus, continuity is established between the outer lead and the CCD. An opaque cover is added next behind the chip and attached to the back of the insulator to prevent undesired light from striking the chip and causing spurious signals. Next, a glass lid is attached to the front surface of the inner leads, protecting the front of the CCD while allowing it to receive light. Finally, J shaped outer leads are formed. The package is substantially wider and thicker than the CCD die mounted in it in order to accommodate the bond wires.
From the aforementioned description of various types of existing CCD packages and their method of fabrication, it is evident that they suffer from one or more limitations and drawbacks. More specifically:
1. The package is substantially wider than the CCD it contains.
2. The package requires many process steps, with ensuing potential defects and added cost associated with each step.
3. The method of packaging requires CCDs to be handled individually before the window is mounted. Physical damage and chemical contaminants are likely to destroy all or part of the CCDs imaging capability before the protective window is mounted.
4. The back grinding process is highly variable, resulting in CCDs substantially thicker or thinner than the desired optimum thickness.
5. Dimensional control in the dicing process is imprecise, and extra width is typically added to the CCD to allow for a margin of error.
The present invention solves the aforementioned problems with a simple, low-cost package made with a well-controlled process.
The invention minimizes the size of the package required for the CCD. The I/O wires are defined on the cover window using, e.g., microlithographic and etching processes that enable wire pitches as small as one um. The fine pitch allows for greater I/O wiring density with the same number of wires in a smaller space than conventional packages.
Another aspect of the present invention is a reduction of the process complexity. The I/O wires and cover plate are attached to the CCD chip simultaneously. The wiring on the cover window is prepared independently of the CCD. The quality of the wiring and window can be verified before assembly. Added advantages are:
Reducing defects by mounting the cover before dicing and handling the individual chips only after the cover window is on
Back grinding thickness control by the use of oxide in a trench for etch stop/endpoint detection
Dicing width control, using oxide trench as an etch channel for dicing
Multiple chip mounting with one single large cover
Wiring on the cover glass
The objects of the invention are met by an integrated chip (IC) package that includes at least one charged-couple device (CCD) chip having a light sensitive surface; and a transparent cover integral to said at least one CCD chip on top of said light sensitive surface.
The integrated chip package preferably has the integrated transparent cover which may take the from of a membrane or an interposer, conformal to the light sensitive surface of the CCD chips. Further, to enhance the wiring capabilities of the IC package wiring is placed in the transparent cover.
The objects of the invention are further achieved by an integrated chip package that includes: a plurality of CCDs integral to a semiconductor wafer, the plurality of CCDs forming an n by m matrix, where n and m are two integers larger or equal to 1, each of the CCDs having a light sensitive surface; and a transparent cover integral to the semiconductor wafer on top of the light sensitive surface of the plurality of CCDs and integral to the semiconductor wafer.
The present invention solves the aforementioned problems with a simple, low-cost package made with a well-controlled process.
The invention minimizes the size of the package required for the CCD. The I/O wires are defined on the cover window using, e.g., microlithographic and etching processes that enable wire pitches as small as one um. The fine pitch allows for greater I/O wiring density with the same number of wires in a smaller space than conventional packages.
Another aspect of the present invention is a reduction of the process complexity. The I/O wires and cover plate are attached to the CCD chip simultaneously. The wiring on the cover window is prepared independently of the CCD. The quality of the wiring and window can be verified before assembly. Added advantages are:
Reducing defects by mounting the cover before dicing and handling the individual chips only after the cover window is on.
Back grinding thickness control by the use of oxide in a trench for etch stop/endpoint detection
Dicing width control, using oxide trench as an etch channel for dicing
Multiple chip mounting with one single large cover.
Wiring on the cover glass
The objects of the invention are met by an integrated chip (IC) package that includes at least one charged-couple device (CCD) chip having a light sensitive surface; and a transparent cover integral to said at least one CCD chip on top of said light sensitive surface.
The integrated chip package preferably has the integrated transparent cover which may take the from of a membrane or an interposer, conformal to the light sensitive surface of the CCD chips. Further, to enhance the wiring capabilities of the IC package wiring is placed in the transparent cover.
The objects of the invention are further achieved by an integrated chip package that includes: a plurality of CCDs integral to a semiconductor wafer, the plurality of CCDs forming an n by m matrix, where n and m are two integers larger or equal to 1, each of the CCDs having a light sensitive surface; and a transparent cover integral to the semiconductor wafer on top of the light sensitive surface of the plurality of CCDs and integral to the semiconductor wafer.